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Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
* Fully integrated PLL * 8 LVCMOS outputs, 7 typical output impedance * Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications * Input/Output frequency range: 18.33MHz to 240MHz at VCC = 3.3V 5% * VCO range: 220MHz to 480MHz * External feedback for "zero delay" clock regeneration * Cycle-to-cycle jitter: 75ps (maximum), (all outputs are the same frequency) * Output skew: 100ps (maximum) * Bank skew: 55ps (maximum) * Full 3.3V or 2.5V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew LVCMOS clock generator and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. With output frequencies up to 240MHz, the ICS8752 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS8752 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
ICS
Dual clock inputs, CLK0 and CLK1, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively. For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. The low impedance LVCMOS outputs of the ICS8752 are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines.
BLOCK DIAGRAM
PLL_SEL PLL FB_IN CLK0 0 CLK1 1 CLK_SEL DIV_SELA1 DIV_SELA0
00 01 10 11 PHASE DETECTOR VCO 1 0 /2 /4 /6 /8 /12 00 01 10 11
PIN ASSIGNMENT
PLL_SEL GND GND VDDO QB3 QB2 VDD nc
32 31 30 29 28 27 26 25 QA0 QA1 QA2 QA3 DIV_SELB0 DIV_SELB1 DIV_SELA0 DIV_SELA1 MR/nOE CLK0 QB0 QB1 QB2 QB3
CLK_SEL VDDA VDD CLK1 GND QA0 QA1 VDDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
GND QB1 QB0 VDDO VDDO QA3 QA2 GND
ICS8752
21 20 19 18 17
GND FB_IN
DIV_SELB1 DIV_SELB0
MR/nOE
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
8752CY
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Description Determines output divider values for Bank B as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. When logic HIGH, the internal dividers are reset and the outputs are Pulldown disabled. When logic LOW, the master reset is disabled and the outputs are enabled. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7, 13, 17, 24, 28, 29 8 9 10 1 1, 32 12 14, 15, 18, 19 16, 20, 21, 25 22, 23, 26, 27 30 31 Name DIV_SELB0, DIV_SELB1 DIV_SELA0, DIV_SELA1 MR/nOE CLK0 GND FB_IN CLK_SEL VDDA VDD CLK1 QA0, QA1, QA2, QA3 VDDO QB0, QB1, QB2, QB3 nc PLL_SEL
Input Input Input Input Power Input Input Power Power Input Output Power Output Unused Input
Pulldown Clock input. LVCMOS / LVTTL interface levels. Power supply ground. Feedback input to phase detector for generating clocks with "zero delay". LVCMOS / LVTTL interface levels. Clock select input. Selects between CLK0 or CLK1 as phase detector Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Pulldown Analog supply pin. Core supply pins. Pulldown Clock input. LVCMOS / LVTTL interface levels. Bank A clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins. Bank B clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. No connect. Pullup Selects between the PLL and CLK0 or CLK1 as the input to the dividers. When HIGH selects PLL. When LOW selects CLK0 or CLK1. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 4 51 51 VDDA, VDD, VDDO = 3.465V 23 7 Maximum Units pF k k pF
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Inputs DIV_ SELA1 X 0 0 1 1 0 0 1 1 0 0 1 1 Outputs DIV_ SELA0 X 0 1 0 1 0 1 0 1 0 1 0 1 DIV_ SELB1 X 0 0 1 1 0 0 1 1 0 0 1 1 DIV_ SELB0 X 0 1 0 1 0 1 0 1 0 1 0 1 QAx Hi-Z fVCO/2 fVCO/4 fVCO/6 fVCO/8 fCLK0/2 fCLK0/4 fCLK0/6 fCLK0/8 fCLK1/2 fCLK1/4 fCLK1/6 fCLK1/8 QBx Hi-Z fVCO/4 fVCO/6 fVCO/8 fVCO/12 fCLK0/4 fCLK0/6 fCLK0/8 fCLK0/12 fCLK1/4 fCLK1/6 fCLK1/8 fCLK1/12
TABLE 3. CONTROL INPUT FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 0 0 0 0
PLL_SEL X 1 1 1 1 0 0 0 0 0 0 0 0
CLK_SEL X X X X X 0 0 0 0 1 1 1 1
NOTE: For normal operation, MR/nOE is LOW. When MR/nOE is HIGH, all ouputs are disabled.
TABLE 4A. QA OUTPUT FREQUENCY
W/FB_IN
= QB
Inputs Outputs DIV_ SELA1 0 DIV_ SELA0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 QA Output Divider Mode /2 /4 /6 /8 /2 /4 /6 /8 /2 /4 /6 /8 /2 /4 /6 /8 QA Multiplier (NOTE 2) 2 1 0.667 0.5 3 1.5 1 0.75 4 2 1.33 1 6 3 2 1.5
FB_IN
DIV_ DIV_ SELB1 SELB0
QB Output Divider Mode (NOTE 2)
CLK0, CLK1 (MHz) (NOTE 1) Minimum Maximum
QB
0
0
/4
55
120
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
QB
0
1
/6
36.66
80
QB
1
0
/8
27.5
60
QB
1
1
/12
18.33
40
NOTE 1: VCO frequency range is 220MHz to 480MHz. NOTE 2: QA output frequency equal to CLKx frequency times the multiplier ; QB output frequency equal to CLKx.
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
W/FB_IN
TABLE 4B. QB OUTPUT FREQUENCY
= QA
Inputs CLK0, CLK1 (MHz) (NOTE 1) Minimum Maximum Outputs DIV_ SELB1 0 DIV_ SELB0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 QB Output Divider Mode /4 /6 /8 /12 /4 /6 /8 /12 /4 /6 /8 /12 /4 /6 /8 /12 QB Multiplier (NOTE 2) 0.5 0.333 0.25 0.167 1 0.667 0.5 0.333 1.5 1 0.75 0.5 2 1.333 1 0.667
FB_IN
DIV_ SELA1
DIV_ SELA0
QA Output Divider Mode (NOTE 2) /2
QA
0
0
110
240 (NOTE 3)
0 1 1 0 0 1 1 0 0 1 1 0 0 1
QA
0
1
/4
55
120
QA
1
0
/6
36.66
80
QA
1
1
/8
27.5
60
1 NOTE 1: VCO frequency range is 220MHz to 480MHz. NOTE 2: QB output frequency equal to CLKx frequency times the multiplier ; QA output frequency equal to CLKx. NOTE 3: Maximum frequency of 240MHz valid for VCC = 3.3V 5% only.
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 105 15 20 Units V V V mA mA mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 100 15 20 Units V V V mA mA mA
8752CY
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V VDDO = VIN = 3.465V VDDO = VIN = 2.625V -5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage DIV_ SELx0, DIV_SELx1, CLK0, CLK1, FB_IN, CLK_SEL, Input High Current MR/nOE PLL_SEL DIV_ SELx0, DIV_SELx1, CLK0, CLK1, FB_IN, CLK_SEL, MR/nOE PLL_SEL VOH Output High Voltage; NOTE 1
IIH
5
A
A
IIL
Input Low Current
-150 2.6 1.8 0.5
A V V V
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, "Output Load Test Circuit" diagrams.
TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Input Reference Frequency NOTE: Input reference frequency is limited by fREF the divider selection and the VCO lock range. Test Conditions Minimum 20 Typical Maximum 240 Units MHz
TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Input Reference Frequency NOTE: Input reference frequency is limited by fREF the divider selection and the VCO lock range. Test Conditions Minimum 20 Typical Maximum 120 Units MHz
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions /2 /4 Minimum 110 55 36.67 27.5 18.33 220 fVCO = 400MHz, Feedback / 8 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 -30 70 Typical Maximum 240 120 80 60 40 480 170 55 100 400 75 1 20% to 80% 400 950 Units MHz MHz MHz MHz MHz MHz ps ps ps ps ps mS ps %
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter
fOUT
Output Frequency (PLL Mode)
/6 /8 /12
fVCO t(O)
PLL VCO Lock Range Static Phase Offset; NOTE 1 Bank Skew; NOTE 2, 4 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise/Fall Time Different Frequencies on Different Banks All Outputs at Same Frequency
tsk(b) tsk(o)
tjit(cc)
tL tR / tF
odc Output Duty Cycle 47 50 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8752CY
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions /2 /4 fOUT Output Frequency (PLL Mode) /6 /8 /12 fVCO t(O) PLL VCO Lock Range Static Phase Offset; NOTE 1 Bank Skew; NOTE 2, 4 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise/Fall Time 20% to 80% 400 Different Frequencies on Different Banks All Outputs at Same Frequency fVCO = 400MHz Feedback / 8 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Minimum 110 55 36.67 27.5 18.33 220 -90 50 Typical Maximum 240 120 80 60 40 480 190 55 90 400 75 1 950 Units MHz MHz MHz MHz MHz MHz ps ps ps ps ps mS ps %
tsk(b) tsk(o)
tjit(cc)
tL tR / tF
odc Output Duty Cycle 45 50 55 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8752CY
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDA,VDDO
SCOPE
Qx
VDD, VDDA,V DDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
(Where X denotes outputs in the same Bank)
2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDO
Qx
2
QX0:QX3
VDDO 2
V
DDO
Qy
2 tsk(o)
QX0:QX3
tsk(b)
VDDO 2
OUTPUT SKEW
BANK SKEW
V
DDO
V
DDO
V
DDO
VDD
QA0:QA3, QB0:QB3 QA0:QA3, QB0:QB3
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2
2
2
CLK0, CLK1
2
tcycle
n
t(O)
1000 Cycles
CYCLE-TO-CYCLE JITTER
V
DDO
STATIC PHASE OFFSET
2 Pulse Width t
PERIOD
Clock Outputs
20% tR tF
odc =
t PW t PERIOD
OUTPUT DUTY CYLCLE/PULSE WIDTH/PERIOD
9
OUTPUT RISE/FALL TIME
REV. B MAY 2, 2005
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tjit(cc) = tcycle n -tcycle n+1
tcycle n+1
FB_IN
VDD 2
80%
80% 20%
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8752 is: 1546 Functionally compatible with MPC952 in some applications
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Marking ICS8752CY ICS8752CY TBD TBD Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8752CY ICS8752CYT ICS8752CYLF ICS8752CYLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8752CY
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REV. B
MAY 2, 2005
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET
Rev A
Table T1
Page 2 1 2 12 2
Description of Change Pin Descriptions Table. Revised MR/nOE description. Features Section - delete bullet, "Industrial temperature available upon request." Added Lead-Free bullet. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Ordering Information Table -added Lead-Free par t number and note. Updated data sheet format. Pin Description Table - correct Pin 5, MR/nOE.
Date 8/19/02
B
T2 T9 T1
3/31/05
B
5/2/05
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REV. B
MAY 2, 2005

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